3D systems are commonly used when it is desired to stack various electronic components one on top of the other. Package on Package (PoP) arrangements are a common example. Typically a top package comprises a processor integrated circuit (IC), while the bottom package comprises a memory IC. Such PoP arrangements are typically used in digital cameras, mobile phones etc. The present invention particularly, but not exclusively, relates to 3D systems in which one or both of the electronic components comprises an integrated circuit.
Typically electronic components are stacked by a machine which collects each component one at time, aligns the current component with the previous component, places the current component on top of the previous component and then collects the next component. Typically the alignment is performed visually. This process is time consuming as it takes time to visually align each component and each component is aligned separately. As the process is time consuming, it is costly.
WO2009/078816 discloses an alignment method in which a plurality of IC dies are mounted to a plurality of ICs provided on a wafer. A positioning member having a plurality of cavities is placed on top of the wafer in a position which aligns the cavities with the ICs of the wafer. The IC dies are then placed into the cavities of the positioning member. The cavities help to align the IC dies with the wafer ICs. The entire disclosure of WO2009/078816 is incorporated herein by reference.
It would be desirable to provide a new method of aligning electronic components; preferably the new method would provide better accuracy and/or speed of alignment.